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Digital Audio Interface Receiver
DESCRIPTION
The WM8803 is a digital audio interface receiver conforming to IEC 60958/61937 and EIAJ CP-1201. It supports input audio data rates up to 192kHz and a maximum output data length of 24 bits. The WM8803 has a flexible digital output port that allows the user access to channel status pre-emphasis information, input signal sampling frequency, sub-code Q data with the associated CRC flags and other status data. The WM8803 can output an externally input clock signal that can be used as an ADC converter clock when the PLL is unlocked. It also maintains the continuity of the output clock when the clock is switched. The WM8803 includes a built-in oscillator and serial data input circuits and allows the system micro-controller to read the sub-code Q data and the channel status. It provides several low-power modes, thus supporting applications that require long battery life, such as portable audio devices and PDAs. The device is available in a 24-pin TSSOP package.
WM8803
FEATURES
* * * * * * PLL circuit for synchronization with transferred input biphase mark signal. Input sampling frequency: 32kHz to 192kHz Outputs clocks: fs, 64fs, and one of 128fs, 256fs, 384fs, and 512fs. 4-Wire CCB MPU Serial Control or Hardware Default Interface Master Clocking Mode Programmable Audio Data Interface Modes - I2S, Left, Right Justified - 16/20/24/32 bit Word Lengths 3.3V Digital supply Operation 5V tolerant digital input ports
* *
APPLICATIONS
* * * * DVD Receivers DVD-R/W Players Audio Video Receivers Portable Music Players
BLOCK DIAGRAM
DI CL CE AUDIO PD
W WM8803
DO
MICROCONTROLLER INTERFACE
DVDD DGND
FS CALCULATOR
E/INT
C&U
UGPI
DEMODULATION AND LOCK DETECTION
RXIN
DATA BUFFER
ERROR
LPF
PLL CLOCK SELECTOR AUDIO INTERFACE
CLKOUT BCLK LRCLK SDATO
XIN
AMP
XOUT AVDD AGND SDIN
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WM8803 TABLE OF CONTENTS
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DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................5 RECOMMENDED OPERATING CONDITIONS .....................................................5 ELECTRICAL CHARACTERISTICS ......................................................................6
INPUT AND OUTPUT PIN CAPACITANCE................................................................... 6 DC CHARACTERISTICS............................................................................................... 6 SYSTEM TIMING REQUIREMENTS ............................................................................. 7 SERIAL INTERFACE TIMING REQUIREMENTS.......................................................... 7 MICRO-CONTROLLER INTERFACE TIMING REQUIREMENTS ................................. 8
DEVICE DESCRIPTION.........................................................................................9
_____
SYSTEM RESET (PD)................................................................................................... 9 LOW POWER MODES ................................................................................................. 9 CLOCKS...................................................................................................................... 11 DATA INPUT AND OUTPUT ....................................................................................... 17 ERROR OUTPUT AND PROCESSING (ERROR)....................................................... 22 CHANNEL STATUS DATA .......................................................................................... 24
__________
USER GENERAL PURPOSE INTERFACE OUTPUT PORT ( UGPI)........................... 24
MICRO-CONTROLLER INTERFACE (E/INT, CE, CL, DI, DO) ...........................28
INTERRUPT OUTPUT (E/INT).................................................................................... 28 CCB ADDRESSES ...................................................................................................... 29 DATA WRITE PROCEDURE....................................................................................... 29 DATA READ PROCEDURE ........................................................................................ 29 I/O TIMING .................................................................................................................. 30 WRITE REGISTER TABLE ......................................................................................... 31 WRITE DATA DETAILED DOCUMENTATION............................................................ 32 READ REGISTER TABLE ........................................................................................... 37 READ DATA DETAILED DOCUMENTATION ............................................................. 38
SAMPLE APPLICATION......................................................................................41 RECOMMENDED EXTERNAL COMPONENTS ..................................................42
RECOMMENDED EXTERNAL COMPONENTS VALUES ........................................... 43
PACKAGE DIMENSIONS ....................................................................................44 IMPORTANT NOTICE ..........................................................................................45
ADDRESS: .................................................................................................................. 45
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WM8803 ORDERING INFORMATION
24 23 22 21 20 19 18 17 16 15 14 13 XIN SDIN SDATO LRCLK BCLK CLKOUT DGND AGND NC LPF AVDD DVDD
DEVICE WM8803SCDT/V TEMP. RANGE -30 to +70oC PACKAGE 24-pin TSSOP
PIN CONFIGURATION
XOUT ERROR PD NC CE CL DI DO E/INT AUDIO UGPI RXIN 1 2 3 4 5 6 7 8 9 10 11 12
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WM8803 PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Notes: 1. 2. 3. Micro-controller register output or clock switching transition period signal. 128fs, 256fs, 384fs, 512fs, or oscillator amplifier outputs Other than I2S mode; I2S mode; 4. 5. Low: right channel, High: left channel Low: left channel, High: right channel NAME XOUT ERROR
PD
5
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TYPE Analogue Output Digital Output Digital Input Digital Input Digital Input Digital Input Digital Input Digital Output Digital Output Digital Output Digital Output Digital Input Supply Supply Analogue Output Supply Supply Digital Output Digital Output Digital Output Digital Output Digital Input Digital Input
DESCRIPTION Oscillation amplifier circuit output pin PLL lock error and data error output pin System reset and low power mode control input pin (5V tolerant) Non connection Micro-controller interface: chip enable input pin (5V tolerant) Micro-controller interface: serial clock input pin (5V tolerant) Micro-controller interface: write data input pin (5V tolerant) Micro-controller interface: read data output pin Pre-emphasis detection or micro-controller interface interrupt output pin Channel status bit 1 non-PCM data detection output pin User general purpose interface output pin1 Digital data input pin (5V tolerant) Digital system power supply Analog system power supply PLL loop filter connection pin No connection Analog system ground Digital system ground System clock output pin2 64fs clock output pin Fs clock output pin3 Demodulated data output pin Serial digital data input pin (5V tolerant) Oscillation amplifier element connection or external clock input pin
NC CE5 CL5 DI5 DO E / INT
AUDIO UGPI
RXIN5 DVDD AVDD LPF NC AGND DGND CLKOUT BCLK LRCLK SDATO SDIN XIN
I/O voltage handling: I or O pins: -0.3 to +3.6V, except annotated pins: -0.3 to +5.5V To prevent logic circuit latch-up, all power supply levels must be applied or removed simultaneously.
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WM8803
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Ele Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically suscept damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage device.
CONDITION Maximum supply voltage Maximum supply voltage Input voltage 1 Input voltage 2 Storage temperature Operating temperature Maximum output current Notes: 1. 2. 3. 4. 5. AVDD pin DVDD pin XIN pin RXIN, SDIN, PD, CE, CL, and DI pins Per single input or output pin
SYMBOL AVDDmax DVDDmax VIN1 VIN2 Tstg Topg Ii, Io
CONDITIONS 1 2 3 4
MIN - MAX -0.3 to 4.6V -0.3 to 4.6V -0.3 to VDD + 0.3V -0.3 to 5.8V -55 to 125C -30 to 70C
5
20 mA
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply voltage 1 Supply voltage 2 Input voltage range 1 Input voltage range 2 Operating temperature Notes: 1. 2. 3. 4. PLLCK [1:0] = "00" or PLLCK [1:0] = "01" PLLCK [1:0] = "10" or PLLCK [1:0] = "11" XIN pin RXIN, SDIN, PD , CE, CL, and DI pins SYMBOL AVDD, DVDD AVDD, DVDD VIN1 VIN2 Topg TEST CONDITIONS 1 2 3 4 MIN 2.7 3.0 0 0 -30 TYP 3.3 3.3 3.3 3.3 -- MAX 3.6 3.6 3.6 5.5 70 UNIT V V V V C
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WM8803 ELECTRICAL CHARACTERISTICS
INPUT AND OUTPUT PIN CAPACITANCE
Test Conditions AVDD = DVDD = VIN1 = VIN2 = 0 V, Ta = 25C, f = 1MHz PARAMETER Input and Output Pin Capacitance Input pins Output pins Notes: 1. AVDD = DVDD = VIN1 = VIN2 = 0 V, Ta = 25C, f = 1MHz CIN COUT 1 1 -- -- -- -- 10 10 SYMBOL TEST CONDITIONS MIN TYP MAX
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UNIT pF pF
DC CHARACTERISTICS
Test Conditions Ta = 25C, AVDD = DVDD = 3.3V, AGND = DGND = 0V PARAMETER DC Characteristics High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage High-level output voltage Low-level output voltage High-level output voltage Low-level output voltage Current drain Current drain Current drain Current drain Notes: 1. CMOS level pins: XIN pin 2. TTL level pins: Input pins other than those listed above. 3. IOH = -8mA, IOL = 6mA: CLKOUT pin 4. IOH = -2mA, IOL = 2mA: BCLK, LRCLK, SDATO, and DO pins 5. IOH = -1mA, IOL = 1mA: Output pins other than those listed above. 6. Operating mode: PLLSEL = "0", AMPOPR = "0", fS = 44.1kHz, CL = 30pF _____ 7. Low power mode condition 1) : PD = low 8. Low power mode condition 2) PDOWN [1:0] = "01", XIN = 11.2896MHz, CL = 30pF 9. Low power mode condition 3) : PDOWN [1:0] = "10", XIN = 11.2896MHz, CL = 30pF VIH VIL VIH VIL VOH VOL VOH VOL VOH VOL IDD1 IDD2 IDD3 IDD4 1 1 2 2 3 3 4 4 5 5 6 7 8 9 0.7DVDD -- 2.0 -0.3 DVDD - 0.8 -- DVDD - 0.8 -- DVDD - 0.8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 6.5 -- 4.5 5 -- 0.2DVDD 5.8 0.8 -- 0.4 -- 0.4 -- 0.4 13 0.1 9 10 V V V V V V V V V V mA A mA mA SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
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WM8803
SYSTEM TIMING REQUIREMENTS
Test Conditions Ta = 25C, AVDD = DVDD = 3.3V, AGND = DGND = 0V PARAMETER System Timing Information RXIN sampling frequency RXIN sampling frequency XIN clock frequency XIN clock frequency XIN clock frequency XIN clock frequency XIN clock frequency XIN clock frequency CLKOUT clock frequency CLKOUT clock jitter Notes: 1. PLLCK [1:0] = "00" 2. Settings other than PLLCK [1:0] = "00". 3. XISEL [3:0] = "0000" 4. XISEL [3:0] = "0001" 5. XISEL [3:0] = "0010" 6. XISEL [3:0] = "0100" 7. XISEL [3:0] = "0101" 8. XISEL [3:0] = "0110" fFS1 fFS2 fXF1 fXF2 fXF3 fXF4 fXF5 fXF6 FMCK tj 1 2 3 4 5 6 7 8 30 30 -- -- -- -- -- -- 2 -- -- -- 11.2896 12.2880 16.9344 22.5792 24.5760 33.8688 -- 200 195 108 -- -- -- -- -- -- 100 -- kHz kHz MHz MHz MHz MHz MHz MHz MHz ps SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
SERIAL INTERFACE TIMING REQUIREMENTS
UGPI
tTKT
CLKOUT tMBO tBDO SDATAO
BCLK
LRCLK
Figure 1 Serial Interface Timing Requirements
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WM8803
Test Conditions Ta = 25C, AVDD = DVDD = 3.3V, AGND = DGND = 0V PARAMETER CLKOUT to BCLK delay BCLK to SDATO delay ____ UGPI low-level pulse width Notes: 1. When setting the clock switching transition period signal output SYMBOL tMBO tBDO tTKT 1 TEST CONDITIONS MIN -- -- -- TYP -- -- --
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MAX 10 5 100
UNIT ns ns ms
MICRO-CONTROLLER INTERFACE TIMING REQUIREMENTS
Test Conditions Ta = -30~70C, AVDD = DVDD = 3.3V, AGND = DGND = 0V PARAMETER SYMBOL TEST CONDITIONS Micro-controller Interface Timing Information
PD low-level pulse width
MIN 200
TYP -- 1/fs -- -- -- -- -- -- -- -- --
MAX -- 63 -- -- -- -- -- -- -- 20 20
UNIT s s ns ns ns ns ns ns ns ns ns
TPDdw TINTuw TCLdw TCLuw tCEsetup TCEhold TDIsetup TDIhold TCLhold tCLtoDO tCEtoDO 1
E/INT high-level pulse width CL low-level pulse width CL high-level pulse width CL to CE setup time CL to CE hold time CL to DI setup time CL to DI hold time CL to CE hold time CL to DO delay time CE to DO delay time Notes:
5 100 100 50 50 50 50 50 -- --
1. INTOPF = "1", INTSEL = "1", and fs is the input sampling frequency.
tINTuw E/INT tCLuw CL tCEsetup tCEhold CE tDIsetup DI tCEtoDO DO Hi-Z tCLtoDO tDIhold tCLhold tCLdw
Figure 2 Micro-controller Interface Timing Requirements
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WM8803
DEVICE DESCRIPTION
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SYSTEM RESET (PD)
The system operates normally when PD is set to high level after applying a supply voltage of 2.7V(3.0V) or higher. Following power ON, the system is reset by setting PD to low level again. System reset is enabled by setting PDB at power on. If a crystal oscillator is used, after setting PD low level and then high level, at least 10ms should be allowed before starting normal operation until the oscillator element is stable.
2.7V VDD t 2.0V PD System reset System operation
t > 200 sec
Figure 3 PD Pin Levels at Power On
LOW POWER MODES
The WM8803 not only supports a total system power down mode controlled with the PD pin but also provides low-power modes in which only certain functions operate. These low power modes are controlled by PDOWN[1:0]. The "power down" mode controlled by the PD pin applies to all circuits in the WM8803. All clocks are stopped and the registers are initialized. The XIN and XOUT pins continue to operate in the PDOWN[1:0] controlled low power mode, which stops all circuits other than the oscillator amplifier. The XOUT signal can be used as the master clock for a DSP or other circuits. The CLKOUT, BCLK, LRCLK, SDATO, SDIN, XIN and XOUT pins continue to operate in the PDOWN[1:0] controlled low power mode, which stops all circuits other than the oscillator amplifier and the divider circuit . This mode can be used to minimize power consumption during analogue data reception. In a low power mode set with the PDOWN[1:0] and with the oscillator amplifier stopped by setting AMPOPR, it will not be possible for the WM8803 to provide a clock output. The AMPOPR overrides all other oscillator settings. Note that the PLLOPR setting is invalid and the PLL circuit will be stopped. When a low power mode is set up with the PDOWN[1:0], it is possible to write to the micro-controller registers. However, all the sub-code Q and channel status data will read out as zeros.
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WM8803
The low power modes are listed in Table 1. MODE (1) (2) (3) (4) H (5) (6) (7) Table 1 Low Power Modes The table below lists the output pin states in the above modes. OUTPUT PIN AUDIOB UGPIB CLKOUT BCLK LRCLK SDATO XOUT ERROR E/INT MODE (1) L H L L L L H H L MODE (2) Output Output Output Output Output Output Output Output Output MODE (3) L Output Output Output Output Output Output H L MODE (4) L Output Output L L L Output H L MODE (5) L Output Output Output Output Output Output H L 0 1 1 x 0 1 1 0 x 0 0 x PDB L AMPOPR x 0 0 0 PLLOPR x 0 1 x PDOWN1 x 0 0 0 PDOWN0 x 0 0 1
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FUNCTION Reset (stand-by) Normal operation VCO stopped. All circuits except the oscillator amplifier stopped. All circuits except the oscillator amplifier and divider circuit stopped. Oscillator amplifier stopped. All circuits stopped.
MODE (6) Output Output Output Output Output Output H Output Output
MODE (7) L Output L L or H L or H L H H L
Table 2 Output Pin States in Modes (1) to (7) Notes: 1. 2. 3. 4. In modes (3), (4), and (5), the clock supplied to XIN is used as the source. Mode (3) applies in the state where an external clock other than CLKOUT is supplied to XIN. If XIN and CLKOUT are connected, no clock signals are output in this mode. Mode (6) applies when the PLL circuit is locked. When the PLL circuit is unlocked, all circuits will go to the stopped state since no clock signal is supplied to XIN. In mode (7), the states immediately prior to entering mode (7) will be retained.
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WM8803
CLOCKS
PLL (LPF)
The WM8803 includes a VCO (voltage controlled oscillator) that can synchronize with data corresponding to sampling frequencies from 30k to 195kHz. The locking frequency is selected by setting PLLCK[1:0]. The VCO circuit can be stopped by setting PLLOPR. The range of input data that can be received depends upon the settings of the PLLCK[1:0]. The (512/2)fs entry for the PLLCK[1:0] = "11" in Table 3 is a state where the PLL itself is synchronized with the 512fs clock, but the clock signal output from CLKOUT is a frequency 1/2 that of the PLL locked frequency i.e.256fs. This (512/2)fs lock frequency has the same functions as the 256fs setting from CLKOUT and can be convenient for certain applications. Refer to the output clocks section for details. It is recommended that the 256fs setting of PLLCK[1:0] = "00" is used to reduce the system power consumption, especially in portable equipment. For best performance, it is recommended that the 512fs setting of PLLCK[1:0] = "10" or the (512/2)fs of PLLCK[1:0] = "11" is used. PLLCK1 0 0 1 1 PLLCK0 0 1 0 1 PLL LOCK FREQUENCY 256fs 384fs 512fs (512/2)fs INPUT DATA RECEPTION RANGE 30k to 195kHz 30k to 108kHz 30k to 108kHz 30k to 108kHz
Table 3 Input Data Reception Ranges by PLL Lock Frequency Setting The LPF is the PLL loop filter connection. Use capacitor and resistor components of the recommended values as listed in the table below according to the PLLCK[1:0] settings used. PLLCK1 0 0 1 1 PLLCK0 0 1 0 1 R0 150 150 C0 0.047F 0.068F C1 0.0068F 0.0047F
Table 4 Loop Filter Component Values
LPF
R0
C1
C0
Figure 4 Loop Filter Structure
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WM8803
OSCILLATOR AMPLIFIER (XIN AND XOUT)
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The following methods can be used to supply a clock signal to the internal oscillator amplifier.
XIN CLKOUT
XIN CLKOUT
XOUT (a) Oscillator element
XOUT
(c) CLKOUT clock signal
XIN CLKOUT
XOUT (b) External clock signal
Figure 5 XIN and XOUT Circuit Structures If an oscillator element is used, it is recommended that it provides the desired system operating frequency as its fundamental frequency. Since the load capacitance depends on the oscillator element characteristics, the circuit must be designed for the crystal used. In normal operation, the clock signal to the XIN pin should be supplied at all times. An externally supplied clock is used when the PLL circuit is unlocked and when XIN is the clock source. A clock source input to XIN is also required when calculating the input data sampling frequency. A clock of frequency 11.2896, 12.288, 16.9344, 22.5792, 24.576, or 33.8688MHz that matches the setting of the XISEL[2:0] should be applied. Digital data should only be input after the XISEL[2:0] has been set to match the oscillator or external clock input frequency. The WM8803 may malfunction if data is input when the input frequency and XISEL[2:0] frequency do not match. The WM8803 will operate even when the frequency set with the XISEL[2:0] and the frequency supplied to XIN differ. However, maintenance of continuity of clock switching and the input fs calculation are not guaranteed. The WM8803 supports an application in which CLKOUT is connected to XIN and XISEL3 is set, thus requiring no oscillator element. However, since only the VCO is used as the source clock, when the PLL is not in the locked state the VCO free-running frequency (10M to 16MHz) will be output from CLKOUT. Furthermore, input fs calculation and limitation are not possible with this technique. Additionally, since no clock is supplied to the oscillator amplifier circuit when the VCO is set to the stopped state, the whole system will go to the stopped state. This function limits settings to PLLCK[1:0] = "00".
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WM8803
The oscillator amplifier normally stops automatically when the PLL is locked, but continuous operation can be set by AMPCNT. Setting the WM8803 to continuous operation mode makes it possible to calculate the input sampling frequency when the PLL is locked. However, since both the oscillator amplifier clock and the PLL clock signals will be present, users must determined whether or not this adversely affects audio quality. The oscillator amplifier can be stopped when not required by setting the AMPOPR. When returning from stopped mode to operating mode the application must maintain its state for at least 10ms until the oscillator stabilizes and normal operation resumes.
OUTPUT CLOCKS (CLKOUT, BCLK, LRCLK)
The clock source for the clock outputs CLKOUT, BCLK, and LRCLK can be selected from two master clocks: the PLL circuit and the XIN pin. Normally, when the PLL circuit is locked master clock is switched to the PLL source. When the PLL circuit is unlocked, master clock automatically switches to the XIN source. The clock source can be forcibly selected by setting OCKSEL. Clock continuity is maintained when the clock source is switched due to the locked/unlocked state of the PLL circuit or by setting OCKSEL. Clock switching depends on the PLL circuit locked/unlocked state at the time OCKSEL is set. If the PLL source is selected by OCKSEL when the PLL circuit is unlocked, the switch will occur automatically after the PLL circuit locks. When VCO operation is stopped by setting PLLOPR, XIN becomes the clock source. However, clock continuity cannot be maintained if the stopped state is set with the PLLOPR while the PLL circuit is locked. Continuity cannot be maintained when switching from the PLL locked state with low power mode set. OCKSEL PLL state Clock source Locked PLL 0 Unlocked XIN Locked XIN 1 Unlocked XIN
Table 5 Command Settings, PLL States, and the Clock Source Either the PLL clock or the XIN clock is output from CLKOUT. The CLKOUT clock signal is divided to create the signals output from BCLK and LRCLK. The frequency when the PLL circuit is locked is set with the PLLCK[1:0]. When switching from the 512fs setting, (PLLCK[1:0] = "10") to the (512/2)fs setting (PLLCK[1:0] = "11") in the PLL locked state, it is possible to maintain clock continuity without losing the PLL lock. This is also true when changing the frequency is the opposite direction.. Using the procedure shown in Figure 6 to switch between 512fs and (512/2)fs, the BCLK and LRCLK output clock will maintain continuity and allow the CLKOUT output clock frequency to be held within a narrow band.
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WM8803
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512fs set Data input
PLLCK0 = 0 PLLCK1 = 1
No
LOCK detection Yes fs = 96 kHz
fs calculation
fs = 48 kHz CLKOUT output 24.576 MHz
(512/2)fs set PLLCK0 = 1 PLLCK1 = 1
Figure 6 Flowchart for CLKOUT Output Clock Narrow Band Operation
The tables below show the output clocks in XIN and PLL clock source modes. PLLCK1 0 0 0 0 0 0 1 1 1 1 1 1 PLLCK0 0 0 0 1 1 1 0 0 0 1 1 1 XISEL1 0 0 1 0 0 1 0 0 1 0 0 1 XISEL0 0 1 0 0 1 0 0 1 0 0 1 0 CLKOUT 11.2896MHz 12.2880MHz 16.9344MHz 11.2896MHz 12.2880MHz 16.9344MHz 11.2896MHz 12.2880MHz 16.9344MHz 11.2896MHz 12.2880MHz 16.9344MHz BCLK 2.8224MHz 3.0720MHz 4.2336MHz 1.8816MHz 2.0480MHz 2.8224MHz 2.8224MHz 3.0720MHz 4.2336MHz 2.8224MHz 3.0720MHz 4.2336MHz LRCLK 44.1kHz 48kHz 66.15kHz 29.4kHz 32kHz 44.1kHz 44.1kHz 48kHz 66.15kHz 44.1kHz 48kHz 66.15kHz
Table 6 XIN Clock Source Mode Output Clocks Note: 1. XISEL2 = 0, PLL unlocked state or forced setting
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WM8803
PLLCK1 0 0 0 0 0 0 1 1 1 1 1 1 PLLCK0 0 0 0 1 1 1 0 0 0 1 1 1 XISEL1 0 0 1 0 0 1 0 0 1 0 0 1 XISEL0 0 1 0 0 1 0 0 1 0 0 1 0 CLKOUT 22.5792MHz 24.5760MHz 33.8688MHz 22.5792MHz 24.5760MHz 33.8688MHz 22.5792MHz 24.5760MHz 33.8688MHz 22.5792MHz 24.5760MHz 33.8688MHz BCLK 5.6448MHz 6.1440MHz 8.4672MHz 3.7632MHz 4.0960MHz 5.6448MHz 5.6448MHz 6.1440MHz 8.4672MHz 5.6448MHz 6.1440MHz 8.4672MHz LRCLK 88.2kHz 96kHz 132.3kHz 58.8kHz 64kHz 88.2kHz 88.2kHz 96kHz 132.3kHz 88.2kHz 96kHz 132.3kHz
Table 7 XIN Clock Source Mode Output Clocks Note: 1. XISEL2 = 1, PLL unlocked state or forced setting PLLCK1 0 0 1 1 PLLCK0 0 1 0 1 CLKOUT 256 s 384fs 512fs 256fs BCLK 64fs 64fs 64fs 64fs LRCLK Fs Fs Fs Fs
Table 8 PLL Clock Source Mode Output Clocks (PLL Locked State) The CLKOUT output clock frequency can be set to 1/2 its normal value by MCKHFO, regardless of the PLL locked/unlocked state. Clock switching using MCKHFO can also be performed in the PLL locked state without losing that locked state, but clock continuity is not maintained. If the audio output format is set to bi-phase data output, the BCLK output clock frequency will be doubled to 128fs when the PLL circuit is locked. However, when unlocked, the BCLK frequencies from Table 8 will be output. Note that the clock continuity is not maintained when this output format is set.
CLOCK SYSTEM DIAGRAM
This section presents the relationship between the two master clock types and the switching and clock dividing functions. The items in square brackets near the switch and function blocks are the names of write commands. The Lock/Unlock switch is switched automatically according to the locked/unlocked state of the PLL circuit.
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WM8803
[PLLOPR] [PLLCK0] [PLLCK1] PLL (256fs) (384fs) (512fs) 512/2fs)
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Lock/Unlock [MCKHFO] [OCKSEL] Divider 1/2 CLKOUT
RXIN
[AMPOPR] [AMPCNT] [XISEL0] [XISEL1] [XISEL2] [XINSET] XIN
Divider 1/2 1/3 1/4 1/6 1/8
BCLK
Divider 1/256 1/384 1/512
LRCLK
XOUT
Figure 7 Master Clock System Diagram
NOTES ON CLOCK SOURCE SWITCHING
In states where the input fs calculation result is restricted by FLIMIT, if the WM8803 is switched by OCKSEL from the PLL locked state (oscillator amplifier stopped) to the XIN source clock state, clock continuity is maintained. However, ERROR will temporarily output a high level indicating an error. This is because the oscillator amplifier will switch to the operating state at the same time as the WM8803 switches to XIN source operation, and the input fs calculation will be restarted. The fs calculated value prior to this time will be reset and when that is compared to the newly calculated fs value, the transition will be handled as a change in fs. With these settings, the oscillator amplifier must be set to continuous operation mode by AMPCNT so that the clock source can be switched by OCKSEL while maintaining the ERROR state. Note that when switching from the oscillator amplifier stopped state to XIN (the clock source while the PLL circuit is locked), clocks which use XIN as the source will be output only after the oscillator amplifier has started operating. Inversely, switching from XIN to the PLL circuit in the locked state allows clocks to be output immediately. In both cases, clock continuity is maintained. When neither an oscillator element nor an external clock is used, but the CLKOUT clock is supplied to XIN. The VCO free-running frequency is output from CLKOUT; when the PLL is unlocked this frequency will be in the range 10 to 16MHz. Clock signals created by dividing CLKOUT are output from BCLK and LRCLK. However, these BCLK and LRCLK clocks will differ with the WM8803 sample rate set and will vary with the supply voltage and operating environment. Care is required when using the CLKOUT, BCLK, and LRCLK clocks when the PLL circuit is unlocked.
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WM8803
DATA INPUT AND OUTPUT
BI-PHASE MARK MODULATED DIGITAL DATA INPUT (RXIN)
The bi-phase mark modulated digital data is input through the RXIN pin. The RXIN pin supports TTL levels. This allows a 5V optical reception module to be connected directly.
BI-PHASE MARK MODULATED INPUT DATA RECEPTION RANGE SETTING
The WM8803 can restrict the upper limit of the input data sampling frequency received and only receive input data at selected sampling frequencies. The input frequency is set by selecting FLIMIT = 1 and selecting the required sampling rate with FSSEL[3:0], Table 9. FSSEL3 0 0 0 0 0 0 0 0 1 1 .... 1 FSSEL2 0 0 0 0 1 1 1 1 0 0 ..... 1 FSSEL1 0 0 1 1 0 0 1 1 0 0 ..... 1 FSSEL0 0 1 0 1 0 1 0 1 0 1 ..... 1 INPUT DATA RECEPTION RANGE 32kHz to 96kHz 32kHz only 44.1kHz only 48kHz only 88.2kHz only 96kHz only 44.1kHz or 88.2kHz only 48kHz or 96kHz only 32kHz or 44.1kHz or 48kHz Reserved
Table 9 Input Data Reception Range (FS4XIN = 0) Note: The notation 32kHz to 96kHz means 32k, 44.1k, 48k, 64k, 88.2k, or 96kHz. The table above only applies when the input fs calculation mode FS4XIN = 0. When FS4XIN = 1, fs data at twice the shown values is supported. Input data that exceeds the set range is handled as an error, and the XIN source clock is output. At this time, the SDATO output data is determined by the RDTSEL setting. When the PLL is following a source with a changing fs, such as a CD player with a variable pitch control, if the oscillator amplifier is stopped with the PLL in the locked state the fs calculation is not performed. As a result, an input frequency outside the set range will not result in an error. The oscillator amplifier must be set to continuous operation mode to handle sources such as this. In systems that connect CLKOUT to XIN and thus do not require an oscillator element, it is not possible to perform the fs calculation. In this mode the reception range cannot be limited.
OUTPUT DATA FORMATS: NORMAL MODE (SDATO)
The output format of audio data is set up after recovery. In Normal Mode the SDATO audio data range can be of the input data format only. The output format is set with the OFSEL[2:0]. The BCLK, LRCLK, and SDATO synchronize to the rising edge of CLKOUT. SDATO is synchronized to the falling edge of BCLK and is clocked on the rising edge. After an error is detected and ERROR goes output low, the output data is synchronized with the LRCLK edge immediately following the Error signal. The ERROR low signal is output for the signal outside the effective bit length of the output data.
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1/fs
Product Preview
LEFT CHANNEL LRCLK
RIGHT CHANNEL
BCLK
SDIN
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
16 to 24 bits
LSB
MSB
16 to 24 bits
LSB
Figure 8 MSB First Left-justified Data Output (OFSEL [2:0] = 000)
1/fs
LEFT CHANNEL LRCLK
RIGHT CHANNEL
BCLK
1 BCLK 1 BCLK 3 n-2 n-1 n 1 2 3 n-2 n-1 n
SDIN
1
2
MSB
16 to 24 bits
LSB
MSB
16 to 24 bits
LSB
Figure 9 I S Data Output (OFSEL [2:0] = 001)
2
1/fs
LEFT CHANNEL LRCLK
RIGHT CHANNEL
BCLK
SDIN
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
16,20,24 bits
LSB
MSB
16,20,24 bits
LSB
Figure 10 MSB First Right-justified Data Output (OFSEL [2:0] = 010,011, or 100)
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OUTPUT DATA FORMATS: SPECIAL MODE (SDATO)
The output format of the audio data is set up after recovery In Special Mode the SDATO audio data range does not necessarily have to match the input data format. The output format is set with the OFSEL[2:0] bit. The BCLK, LRCLK, and SDATO synchronize to the rising edge of CLKOUT. SDATO is synchronizes to the falling edge of BCLK and is clocked on the rising edge. After an error is detected and ERROR goes output low, the output data is synchronized with the LRCLK edge immediately following the error signal. Bi-phase data output synchronizes to LRCLK and the fs clock of the 128fs clock. However, when the PLL is unlocked the BCLK changes to the 64fs clock, Figure 8. The NRZ 28bits data output contains 4 bits validity (V), user data (U), channel status (C), preamble B (indicated by Z) and 24bit LSB left justified base audio data. When preamble B is confirmed Z-bit outputs high in that frame, Figures 9 and 10. A ERROR low signal is output for a signal outside the effective bit length of the NRZ data output.
LRCLK
L-ch
R-ch
BCLK SDATAO
C P
LSB MSB V
UCP
LSB
MSB V
UCP
Figure 11 Data Output Timing - Biphase Data Output
LRCLK
L-ch
R-ch
BCLK SDATAO
LSB -24 bitMSB VUC Z LSB -24 bitMSB VUC Z
28 bits
28 bits
Notice: `Z' means Preamble `B'
Figure 12 Data Output Timing - NRZ Data I2S Output
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LRCLK
L-ch
R-ch
BCLK
LSB -24 bitMSB VUC Z LSB -24 bitMSB VUC Z
SDATAO 28 bits 28 bits
Notice: `Z' means Preamble `B'
Figure 13 Data Output Timing - NRZ Data LSB First Left-justified Output
SERIAL AUDIO DATA INPUT FORMAT (SDIN)
The SDIN pin is a serial digital audio data input that can accept 24bit data data from sources such as an A/D converter output. When the data input to the SDIN is output from the SDATO, a clock signal synchronized with the SDIN input data must be output from the BCLK and LRCLK to produce useable signals. Except for the Special Mode setting, the SDIN input must have the same format as the required output data format.
1/fs
LEFT CHANNEL LRCLK
RIGHT CHANNEL
BCLK
SDIN
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
16 to 24 bits
LSB
MSB
16 to 24 bits
LSB
Figure 14 MSB First Left-justified Data Input
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WM8803
1/fs
LEFT CHANNEL LRCLK
RIGHT CHANNEL
BCLK
1 BCLK 1 BCLK 3 n-2 n-1 n 1 2 3 n-2 n-1 n
SDIN
1
2
MSB
16 to 24 bits
LSB
MSB
16 to 24 bits
LSB
Figure 15 I2S Data Input
1/fs
LEFT CHANNEL LRCLK
RIGHT CHANNEL
BCLK
SDIN
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
16,20,24 bits
LSB
MSB
16,20,24 bits
LSB
Figure 16 MSB First Right-justified Data Input
OUTPUT DATA SWITCHING (SDIN, SDATO)
The SDATO pin outputs the demodulated data when the PLL circuit is locked and the SDIN input data when the PLL circuit is unlocked. Switching between SDIN and SDATO is performed automatically according to the locked/unlocked state of the PLL circuit. When XIN is the clock source, input data synchronized with the CLKOUT, BCLK, and LRCLK clocks as the SDIN input data. The SDIN input data can be output from SDATO by setting RDTSTA regardless of the PLL circuit locked/unlocked state. In this case, the CLKOUT, BCLK, and LRCLK clocks will also be switched to the XIN clock source. The switch occurs in synchronization with the LRCLK edge that follows the setting of the RDTSTA. The SDATO output data can be forcibly muted by setting RDTMUT. The muting processing is started in synchronization with the LRCLK edge that follows the setting of the RDTMUT. The SDATO output can be muted in the PLL locked state by setting RDTSEL. These settings have the following priority order: RDTSEL < RDTSTA < RDTMUT.
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Product Preview When XIN is set to be the clock source with OCKSEL, the PLL circuit will operate as long as PLL operation is not stopped by PDOWN[1:0] or PLLOPR. In this mode the state of the PLL circuit is always output from the ERROR pin. Regardless of the PLL state information processed can be read out over the micro-controller interface.
PLL locked state UGPI ERROR SDATAO
UNLOCK
LOCK
UNLOCK
SDIN data
Muted
Demodulated data
Muted
SDIN data
UGPI: When the clock switching transition period signal is selected
Figure 17 SDATO Output Data Switching Timing Chart (when RDTSEL is set to "0")
INPUT DATA SAMPLING FREQUENCY CALCULATION
This function calculates the input data sampling frequency using the XIN clock. In modes where the oscillator amplifier is automatically stopped due to PLL circuit lock, the fs calculation is performed and ERROR indicates the error state. Calculation completes at the same time the oscillator amplifier is stopped and the fs value is retained. After calculation is confirmed, the value does not change until the PLL circuit goes to the unlocked state. In continuous operation mode, the oscillator amplifier continuously repeats the frequency calculation. Even when sampling the input data during which the channel status sampled information does not change within the PLL capture range, it will still be possible to read out a calculated result that follows the input data. The calculated result can be read out from CCB address 0xEC or output registers DO4 to DO6. Note, however, that when the PLL synchronizes with data that corresponds to 32k to 192kHz. The fs calculation mode can be selected from two modes; a 32k to 96kHz calculation mode and a 64k to 192kHz calculation mode and is switched by FS4XIN. It is not possible to monitor an fs calculation result for the whole 32k to 192kHz range at the same time. In systems that connect CLKOUT to XIN and thus do not require an oscillator element, the fs calculation result will always be "out of range".
ERROR OUTPUT AND PROCESSING (ERROR)
LOCK ERROR AND DATA ERROR OUTPUT
The ERROR pin outputs a high level when the PLL is in the unlocked state or an error occurs in the transmitted data.
PLL LOCK ERROR
The PLL circuit will go to the unlocked state for input data that does not conform to the bi-phase modulation rules and for input data in which the preamble B, M, and W cannot be detected. The ERROR output goes to the high level when a PLL lock error occurs and is held high until data modulation has returned to normal for 15 to 50ms. The rise and fall of the ERROR output is synchronized with LRCLK.
INPUT DATA TRANSMISSION ERROR
Odd input parity errors are detected from the parity bits in the input data. When input parity errors occur for 9 or more consecutive cycles, the ERROR output goes high. The high level is held until the PLL is in a locked state for 15 to 50ms, then ERROR returns low. When 8 or fewer consecutive input parity errors occur, an error will only be output for intervals between sub-frames for errors that occurred only when non-PCM data is recognized by the channel
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WM8803
status data delimiter bit 1. In this case, the parity error flag used for data recognized as PCM data will not be output.
OTHER ERRORS
Even when ERROR has gone low, the WM8803 always acquires bits 24 to 27 (sampling frequency) of the channel status and compares the current data with that of the previous block. If any differences are found, ERROR is immediately set to the high level and the state is handled as a PLL lock error. Similarly, when FLIMIT is set to restrict fs input range and the input fs calculation results are reflected in the error flags, fs calculation results are compared continuously. If a disparity occurs in the data, ERROR will immediately go high, and the state will be handled as a PLL lock error.
ERROR OCCURRENCE PROCESSING
This section describes the data processing performed when an error occurs. When up to 8 consecutive input parity errors occur and if the transmitted data is PCM audio data, the data is replaced with the corresponding left and right channel data from the immediately preceding frame. If the transmitted data is non-PCM data, the error data is output without modification. Non-PCM data is based on data that was detected before the input parity error that occurred, and is data for which the channel status bit 1 non-PCM data detection bit is "1". The output data is muted when 9 or more consecutive parity errors, or a PLL lock error, occur. For the channel status output when a parity error occurs, the data for the previous block is retained. DATA AND DETECTION FLAGS SDATO output pin Input fs calculation Channel status data Sub-code Q data PLL LOCK ERROR L L L L INPUT PARITY ERROR (A) L L L L INPUT PARITY ERROR (B) Previous data Output Previous data Output INPUT PARITY ERROR (C) Output Output Previous data --
Table 10 Data Processing when Errors Occur Notes: 1. 2. 3. Input parity error (A): When 9 or more consecutive parity errors occur Input parity error (B): When up to 8 consecutive parity errors occur in audio data Input parity error (C): When up to 8 consecutive parity errors occur in non-PCM burst data
The figure below presents an example of the data processing performed when a parity error occurs.
An error occurs a single time Input Data L-1 R-1 L-2 R-2 L-3 R-3 L-4 R-4 L-5 R-5 L-6 R-6 L-7 R-7 L-8 R-8
ERROR
LRCLK SDATAO L-0 R-0 L-1 R-0 L-2 R-2 L-2 R-2 L-2 R-2 L-2 R-2 L-2 R-2
R-ch L-ch R-ch .... Previous data value Previous data value Muted after 9 or more consecutive errors
Figure 18 Data Processing Example Following a Parity Error (When PCM data is received)
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ERROR RECOVERY PROCESSING
Product Preview
When the preamble B, M, and W are detected, the PLL circuit goes to the locked state and data demodulation starts. The SDATO output data starts on the first LRCLK edge after ERROR goes low.
15 ms to 50 ms ERROR OK Internal clock signal LRCLK
SDATAO
Data
Output starts from the LRCK edge immediately following the fall of the ERROR flag
Figure 19 Data Processing at the Start of Data Demodulation
CHANNEL STATUS DATA
DATA DELIMITER BIT 1 OUTPUT ( AUDIO )
AUDIO outputs the channel status bit 1, which indicates whether or not the input bi-phase data is PCM audio data. AUDIO
OUTPUT CONDITIONS PCM audio data (CS bit 1 = low) Non-PCM data (CS bit 1 = high)
L R Table 11 AUDIO Output
EMPHASIS INFORMATION OUTPUT (E/INT)
E/INT has a shared function as a micro-controller interface interrupt output or, in the initial settings state, it outputs the presence or absence of emphasis of the input signal. This emphasis has a time constant of 50/15s for use in consumer products or broadcast studios. E/INT L R Table 12 E/INT Output
__________
OUTPUT CONDITIONS No pre-emphasis 50/15s pre-emphasis
USER GENERAL PURPOSE INTERFACE OUTPUT PORT ( UGPI)
UGPI is a user-settable output port that supports the following functions.
-- --
Micro-controller interface register output Clock switching transition period signal output
GPISEL selects between these functions. In the initial settings, the micro-controller interface register GPIDAT is allocated to this pin. The initial setting of the GPIDAT register is 1, so a high level will be output from UGPI .
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WM8803
MICRO-CONTROLLER INTERFACE REGISTER OUTPUT (OPTICAL RECEIVER MODULE POWER DOWN EXAMPLE)
This section describes an example in which UGPI outputs a micro-controller interface register, and how that signal is used as the power supply control signal for an optical receiver module. 1. 2. 3. Connect the UGPI output to the optical receiver module power supply control switch.
_____
After clearing a reset due to PD , the micro-controller interface register output will be selected as the initial setting for UGPI . As a result, the GPIDAT set value will be output. After a reset is cleared, the initial value of GPIDAT = 1, and so UGPI will be output high. The control switch will be in the off state, and data will not be supplied from the optical receiver module. Setting GPIDAT = 0 will activate the optical receiver module supply data. Controlling the UGPI output with GPIDAT will allow current drain to be minimized when the optical receiver module is not used.
4.
WM8803
UGPI
RXIN
Optical receiver module
Figure 20 UGPI Output Example (Optical Receiver Module Power Supply Control)
MICRO-CONTROLLER INTERFACE REGISTER OUTPUT (DIGITAL DATA INPUT SWITCH CONTROL SIGNAL EXAMPLE)
UGPI , when used as a micro-controller interface register output, can be used as a control signal that switches the digital data input.
If more than one type of data input is required an input selector circuit and a control signal will be required. It is possible to implement two digital data inputs without having to provide a control signal from the micro-controller by using the UGPI output. Note that after a reset is cleared, the initial value of GPIDAT will be 1, and as a result, UGPI will output a high level.
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WM8803
UGPI
SW RXIN
Figure 21 UGPI Output Usage Example (Data Input Switching Example)
CLOCK SWITCHING TRANSITION PERIOD SIGNAL OUTPUT
This section describes operation when UGPI is selected as the clock switching transition period signal. When there are changes to the PLL circuit locked/unlocked state, the clock switching transition period signal reports to external circuits the output clock state switching transitions. This signal allows the application to grasp the PLL lock state transitions and the timing of changes in the clock signals. GPISEL is used to select this function. After setting GPISEL, UGPI will initially output a high level. This is followed by output low level pulses when the output clock changes due to changes in the PLL circuit locked/unlocked state. In the lock pull-in process, the UGPI falling edge is triggered by the word clock generated by the XIN clock after input data is detected and the PLL circuit locks, and by UGPI rising with the same timing as ERROR after a fixed period has elapsed. In the process where the PLL lock state is lost, the UGPI low level pulse is formed by UGPI falling with the same timing as the PLL lock detection signal ERROR and by UGPI rising after a fixed number of counts of the word clock generated from XIN.
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WM8803
Digital Data Unlocked Locked
RXIN PLL Lock State XTAL Clock VCO Clock
UGPI ERROR
After PLL lock
15 ms to 50 ms With the same timing as ERROR
CLKOUT (a) During the lock pull-in process
RXIN PLL Lock State XTAL Clock VCO Clock
Digital Data Locked Unlocked
64/fs (sec)
UGPI
With the same timing as ERROR
ERROR CLKOUT (b) During the loss of PLL lock
Figure 22 Clock Switching Timing
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WM8803 MICRO-CONTROLLER INTERFACE (E/INT, CE, CL, DI, DO)
INTERRUPT OUTPUT (E/INT)
Product Preview
The E/INT pin can be set to function as the micro-controller interface interrupt output using INTSEL. An interrupt is issued when a change occurs in the PLL lock state, the output data information or other aspects of WM8803 operation. The interrupt output function consists of registers for selecting interrupts, the E/INT pin to output those state transitions, and the registers that store interrupt related data. The E/INT pin normally outputs a low level, but outputs a high level when an interrupt occurs. After outputting a high level, it returns to the low level according to the INTOPF setting. INTOPF selects whether the E/INT pin holds the high level for a fixed period and then is cleared (returning to the low level), or is cleared at the same time as the output register is read. The interrupts can be selected from the items listed in Table 13. More than one of these items can be set to be interrupts at the same by setting the contents of CCB address 0xEA. The interrupt signal is issued whenever any one of the interrupt events occurs. E/INT output = (selected interrupt 1) + (selected interrupt 2) + ... + (selected interrupt n) NO. 1 2 3 4 5 6 7 COMMAND INTERR INTPCM INTEMP INTVFL INTFSC INTCSF INTSQY DESCRIPTION Output when the state of the ERROR pin changes. Output when the state of the AUDIO pin changes. Output when the state of the pre-emphasis information changes. Output when the state of the validity flag changes. Output when the input fs calculation result changes. Output when the first 48 bits of the channel status data is updated. Output when the sub-code Q data can be read out.
Table 13 Interrupt Event Settings When an interrupt event occurs the content of the selected interrupt events is stored in the CCB address 0xEB output registers DO1 to DO7. The read registers for event items 1 through 4 read out the current state of those events regardless of the E/INT output. For event items 5 through 7, the state is stored when the event occurs. To monitor interrupt event item 5 in the PLL locked state, the oscillator amplifier must be set to continuous operation mode, since the oscillator amplifier clock is used. When E/INT is set to output a high-level pulse when interrupt event occurs, the pulse width for each interrupt event will be between 1/2 fs and 3/2 fs. When the WM8803 is set so that E/INT is cleared after the output register is read, the clear operation is performed immediately after output register 0xEB is reset. The data for interrupt events 6 and 7 is updated within the periods shown in Table 14, the corresponding read registers should be read as soon as possible after the event is detected. DATA Channel status and preamble B Sub-code Q data Table 14 Data Update Intervals (Input fs = 32k to 96kHz) UPDATE INTERVAL 2ms to 6ms 13.3ms (fs = 44.1kHz), 6.65ms (2x speed)
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CCB ADDRESSES
The address locations in Table 15 are those used to set the parameters, write data values and to read data values from the WM8803 over the micro-controller interface. The micro-controller interface data format conforms to that of the Sanyo-developed CCB serial bus format. However, a three state circuit is adopted for the data output instead of the open drain circuit used in CCB. Data is input or output after input of the CCB address. See the I/O timing chart for details on the data input and output timing. CCB ADDRESS 0xE8 0xE9 0xEA 0xEB 0xEC 0xED
REGISTER CONTENT Function settings data 1 Function settings data 2 Function settings data 3 Interrupt data output Fs value, CS data output Sub-code Q data output
R/W Write Write Write Read Read Read
B0 0 1 0 1 0 1
B1 0 0 1 1 0 0
B2 0 0 0 0 1 1
B3 1 1 1 1 1 1
A0 0 0 0 0 0 0
A1 1 1 1 1 1 1
A2 1 1 1 1 1 1
A3 1 1 1 1 1 1
Table 15 Register I/O Content and CCB Addresses
DATA WRITE PROCEDURE
The data input bit length is 16 bits. After inputting data to one of the CCB addresses 0xE8 to 0xEA, set CE to the high level. Input data is acquired on the rising edge of CL. The bits marked "0" in the table are reserved bits. A value of 0 must be written to these bits.
DATA READ PROCEDURE
Read data is output from DO and goes to the high-impedance state when CE is low. Output starts on the CE rising edge following the establishment of the output address by the CCB command on the DI pin. After operation the DO pin is returned to the high-impedance state by setting CE low. The number of data bits read out differs with the type of data read. Interrupt data has 8bits, the channel status related data (0xEC) has 56bits, and the sub-code Q data (0xED) has 88bits. However, it is not necessary to read out all the data. During readout it is possible to read data up to the point when the CL clock is stopped and the CE pin is set low. For example, when reading the sub-code Q data, if the CRC flags are read and the data is seen to be corrupted, there is no need to read the data following.
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I/O TIMING
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CE
CL DI DO B0 B1 B2 B3 A0 A1 A2 A3 DI0 DI1 DI2 DI3 DI4 DI5 .... DI15
Hi-Z
Figure 23 Input Timing Chart (Normal, Low Clock)
CE CL
DI
B0
B1
B2
B3
A0
A1
A2
A3
DI0 DI1 DI2 DI3 DI4 DI5 ....
DI15
DO
Hi-Z
Figure 24 Input Timing Chart (Normal, High Clock)
CE
CL DI DO B0 B1 B2 B3 A0 A1 A2 A3 DO1 DO2 DO3 DO4 .... .... DOn
Hi-Z
DO0
Figure 25 Output Timing Chart (Normal, Low Clock)
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CE CL
DI
B0
B1
B2
B3
A0
A1
A2
A3 DO0 DO1 DO2 DO3 DO4 .... .... .... DOn
DO
Hi-Z
Figure 26 Output Timing Chart (Normal, High Clock) Note:
1.
It is necessary to read DO0 with a separate port from DI.
WRITE REGISTER TABLE
The table below lists the write registers.
INPUT REGISTER 0XE8 0XE9 0XEA
DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI10 DI11 DI12 DI13 DI14 DI15
Table 16 List of Write Registers
SYSRST 0 PDOWN0 PDOWN1 PLLOPR PLLCK0 PLLCK1 MCKHFO 0 AMPOPR AMPCNT OCKSEL XISEL0 XISEL1 XISEL2 XISEL3
GPISEL GPIDAT FLIMIT FS4XIN FSSEL0 FSSEL1 FSSEL2 FSSEL3 OFSEL0 OFSEL1 OFSEL2 0 RDTSEL RDTSTA RDTMUT 0
INTOPF 0 0 0 0 0 0 0 INTSEL INTERR INTPCM INTEMP INTVFL INTFSC INTCSF INTSQY
The shaded areas are reserved bits. Only a value of 0 may be written to these bits.
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WRITE DATA DETAILED DOCUMENTATION
DI7 DI6 DI5 DI4 DI3 DI2 DI1
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DI0
MCKHFO
DI15
PLLCK1
DI14
PLLCK0
DI13
PLLOPR
DI12
PDOWN1
DI11
PDOWN0
DI10
0
DI9
SYSRST
DI8
XISEL3
XISEL2
XISEL1
XISEL0
OCKSEL
AMPCNT
AMPOPR
0
Table 17 Input Register Function Settings 1: System Settings (0xE8) SYSRST: System reset
0: No reset performed (initial value) 1: Reset all circuits other than the command registers.
PDOWN[1:0]:
Low power mode settings (Allows the operation of specific functions only)
00: Normal operation (initial value) 01: Only the oscillator amplifier operates. 10: Only the oscillator amplifier and the output clock divider operate. 11: Reserved
PLLOPR:
PLL (VCO) operate/stop setting
0: Operate (initial value) 1: Stop
PLLCK[1:0]:
PLL locked state clock frequency setting
00: 256fs (initial value) 01: 384fs 10: 512fs 11: (512/2)fs = 256fs
MCKHFO:
CLKOUT output clock frequency setting
0: 1/1 output (initial value) 1: 1/2 output
In the PLL locked state when switching from the 512fs setting with the PLLCK[1:0] = "10" to the (512/2)fs setting with the PLLCK[1:0] = "11" it is possible to maintain clock continuity without entering the PLL lock error state..This is also the case when switching in the reverse direction. For systems such as portable equipment power consumption can be minimized,by setting PLLCK[1:0] = "00" (256fs). Systems such as AV amplifiers that required best performance, the PLLCK[1:0] = "10" (512fs) or the PLLCK[1:0] = "11" (512/2fs) setting is recommended.
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AMPOPR: Oscillator amplifier operate/stop setting
0: Operate (initial value) 1: Stop
AMPCNT:
Oscillator amplifier state setting
0: Automatically stop in the PLL locked state (initial value) 1: Always operate
OCKSEL:
Clock source setting
0: Use the XIN clock as the source when the PLL is unlocked (initial value) 1: Use the XIN clock as the source regardless of the PLL state.
XISEL[3:0]:
XIN input frequency setting
0000: 11.2896MHz (initial value) 0001: 12.288MHz 0010: 16.9344MHz 0011: Reserved 0001: 22.5792MHz 0010: 24.576MHz 0010: 33.8688MHz 0011: Reserved 1xxx: Setting used when the CLKOUT pin and the XIN pin are connected.
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DI7 DI6 DI5 DI4 DI3 DI2 DI1
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DI0
FSSEL3
DI15
FSSEL2
DI14
FSSEL1
DI13
FSSEL0
DI12
FS4XIN
DI11
FLIMIT
DI10
GPIDAT
DI9
GPISEL
DI8
0
RDTMUT
RDTSTA
RDTSEL
0
OFSEL2
OFSEL1
OFSEL1
Table 18 Input Register Function Settings 1: I/O Data Settings (0xE9) GPISEL:
UGPI pin setting
0: Outputs the micro-controller interface register state. (initial value) 1: Outputs the clock switching transition period signal.
GPIDAT:
UGPI pin setting (Only valid when register output mode is set up)
0: Outputs the low level. 1: Outputs the high level. (initial value)
FLIMIT:
Input data reception limitation setting
0: No reception limitation. All data within the PLL locking range can be received. (initial value) 1: Reception is limited. The input fs calculation result is reflected in the error flag according to the FSSEL[3:0] setting.
FS4XIN:
Input fs calculation range setting
0: Perform fs calculation for input data in the range 32k to 96 kHz. (initial value) 1: Perform fs calculation for input data in the range 64k to 192 kHz.
FSSEL[3:0]:
Input data reception range setting (When FLIMIT = "1" and FS4XIN = "0")
0000: 32k, 44.1k, 48k, 64k, 88.2k, or 96kHz (initial value) 0001: 32kHz only 0010: 44.1kHz only 0011: 48kHz 0100: 88.2kHz only 0101: 96kHz only 0110: 44.1k or 88.2kHz only 0111: 48k or 96kHz only 1000: 32k or 44.1k or 48kHz 1001-1111:Reserved
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WM8803
FSSEL[3:0]: Input data reception range setting (When FLIMIT = "1" and FS4XIN = "1")
0000: 64k, 88.2k, 96k 128k, 176.4k, or 192kHz (initial value) 0001: 64kHz only 0010: 88.2kHz only 0011: 96kHz only 0100: 176.4kHz only 0101: 192kHz only 0110: 88.2k or 176.4kHz only 0111: 96k or 192kHz only 1000: 64k or 88.2k or 96kHz only 1001-1111: Reserved
OFSEL[2:0]:
Serial audio data output format setting
000: 24-bit MSB first left-justified data output (initial value) 001: 24-bit I2S data output 010: 24-bit MSB first right-justified data output 011: 20-bit MSB first right-justified data output 100: 16-bit MSB first right-justified data output 101-100: Reserved 101: Bi-phase data output 110: 28-bit I2S data output (NRZ data output) 111: 28-bit LSB first left-justified data output (NRZ data output)
RDTSEL:
SDATO output setting in the PLL unlocked state
0: Output the SDIN data in the PLL unlocked state. (initial value) 1: Mute the output in the PLL unlocked state.
RDTSTA:
SDATO output setting
0: Observe the RDTSEL setting. (initial value) 1: Output the SDIN data regardless of the PLL state.
RDTMUT:
SDATO mute setting
0: Output the data selected by RDTSEL. (initial value) 1: Mute the output.
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WM8803
DI7 DI6 DI5 DI4 DI3 DI2 DI1
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DI0
0
DI15
0
DI14
0
DI13
0
DI12
0
DI11
0
DI10
0
DI9
INTOPF
DI8
INTQSY
INTCSF
INTFSC
INTVFL
INTEMP
INTPCM
INTERR
INTSEL
Table 19 Input Register Function Settings 1: Interrupt Settings (0xEA) INTOPF: E/INT output setting (Only valid when the interrupt output function is selected.)
0: Output a high level when an interrupt occurs. (initial value) 1: Output a high level pulse when an interrupt occurs.
INTSEL:
E/INT pin setting
0: Output the channel status emphasis information. (initial value) 1: Output the micro-controller interface interrupt signal.
INTERR:
ERROR signal output setting
0: Do not output this signal. (initial value) 1: Output changes to the ERROR pin state.
INTPCM:
AUDIO signal output setting
0: Do not output this signal. (initial value) 1: Output changes to the AUDIO pin state.
INTEMP:
Channel status emphasis detection flag output setting
0: Do not output this flag. (initial value) 1: Output the emphasis detection flag.
INTVFL:
Parity flag detection flag output setting
0: Do not output this flag. (initial value) 1: Output the parity flag.
INTFSC:
PLL lock frequency calculation result update flag output setting
0: Do not output this flag. (initial value) 1: Output the PLL lock frequency calculation result update flag.
INTCSF:
First 48 bits of channel status data update flag output setting
0: Do not output this flag. (initial value) 1: Output the first 48 bits of channel status data update flag.
INTQSY:
Sub-code Q data readout load signal detection flag output setting
0: Do not output this flag. (initial value) 1: Output the flag that indicates updates to the 80 bits of sub-code Q data including the CRC.
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WM8803
If E/INT is set up for high level output when an interrupts are generated with INTOPF, the high-level state will be maintained until the interrupt event output (address 0xEB) is read out. When that data has been read, the E/INT output will return to the normal low level. The channel status update flag is computed by comparing the current data with the first 48bits of the previous block, and determining the channel status to have been updated if the data is the same.
READ REGISTER TABLE
The table below lists the read registers.
OUTPUT REGISTER 0XEB 0XEC 0XED
DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9 DO10 DO11 DO12 DO13 DO14 DO15 DO16 DO17 DO18 DO19 DO20 DO21 DO22 DO23 DO24 ..... DO54 DO55 DO56 ..... DO86 DO87
Table 20 List of Read Registers
0 OUTERR OUTPCM OUTEMP OUTVFL OUTFSC OUTCSF OUTSQY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 OUTERR OUTPCM 0 FSCAL0 FSCAL1 FSCAL2 0 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Bit 16 ..... Bit 46 Bit 47 0 0 0 0
CRC CRC 0 0 0 0 0 0 Control Control Control Control Address Address Address Address Track Track Track Track Track Track Track Track Index ..... Frame Frame zero ..... abs frame abs frame
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READ DATA DETAILED DOCUMENTATION
DO7 DO6 DO5 DO4 DO3 DO2 DO1
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DO0
OUTSQY
OUTCSF
OUTFSC
OUTVFL
OUTEMP
OUTPCM
OUTERR
0
Table 21 Output Register: Interrupt Data Output (0xEB) OUTERR: ERROR output (Outputs the state when read)
0: No transmission error and the PLL circuit is in the PLL locked state. 1: Either a transmission error occurred or the PLL circuit is in the unlocked state.
OUTPCM:
AUDIO output (Outputs the state when read)
0: Non-PCM signal not detected. 1: Non-PCM signal detected.
OUTEMP:
Channel status emphasis detection (Outputs the state when read)
0: No pre-emphasis. 1: 50/15s pre-emphasis was applied.
OUTVFL:
Parity flag detection (Outputs the state when read)
0: No error. 1: Parity error detected.
OUTFSC:
Input fs calculation result (Cleared after read)
0: No input fs calculation result update. 1: The fs calculation result was updated.
OUTCSF:
First 48 bits of the channel status update result (Cleared after read)
0: This data was not updated. 1: The data has been updated.
OUTQSY:
Sub-code Q data readout load signal detection (Cleared after read)
0: Not detected. 1: Detected.
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WM8803
DO7 DO6 FSCAL2 DO5 FSCAL1 DO4 FSCAL0 DO3 0 DO2 OUTPCM DO1 OUTERR DO0 0
0 8 16 24 32 40 48
0
Bit 7 Bit 15 Bit 23 Bit 31 Bit 39 Bit 47
Bit 6 Bit 14 Bit 22 Bit 30 Bit 38 Bit 46
Bit 5 Bit 13 Bit 21 Bit 29 Bit 37 Bit 45
Bit 4 Bit 12 Bit 20 Bit 28 Bit 36 Bit 44
Bit 3 Bit 11 Bit 19 Bit 27 Bit 35 Bit 43
Bit 2 Bit 10 Bit 18 Bit 26 Bit 34 Bit 42
Bit 1 Bit 9 Bit 17 Bit 25 Bit 33 Bit 41
Bit 0 Bit 8 Bit 16 Bit 24 Bit 32 Bit 40
Table 22 Output Register: Input fs Calculation Result and Channel Status Data (0xEC)
Error information, non-PCM information, input fs calculation result, and channel status data can be read from this register. Note that the error information and the non-PCM data information are the same as those read from 0xEB.
OUTERR:
ERROR output (Outputs the state when read)
0: No transmission error and the PLL circuit is in the PLL locked state 1: Either a transmission error occurred or the PLL circuit is in the unlocked state.
OUTPCM:
AUDIO output (Outputs the state when read)
0: Non-PCM signal not detected. 1: Non-PCM signal detected.
The input data fs calculation result is allocated as shown in Table 23. The target calculation frequencies differ depending on the FS4XIN setting. The calculation range differs slightly depending on the XIN clock frequency.
FS4XIN = 0 FSCAL2 FSCAL1 FSCAL0 TARGET FS CALCULATED RANGE TARGET FS FS4XIN = 1 CALCULATED RANGE
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Out of range 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz --
-- 30.9k to 33.2kHz 42.5k to 45.8kHz 46.3k to 49.9kHz 62.1k to 66.4kHz 85.6k to 91.0kHz 92.6k to 99.0kHz --
Out of range 64kHz 88.2kHz 96kHz 128kHz 176.4kHz 192kHz --
-- 62.0k to 66.4kHz 85.5k to 91.0kHz 92.6k to 99.0kHz 124.0k to 132.8kHz 171.0k to 182.2kHz 185.1k to 198.0kHz --
Table 23 Input fs Calculation Result (Ta = 25C, VDD = 3.3V, XIN = 11.2896MHz)
The channel status reads out the first 48bits of the data. Since the channel status consists of 192 frames, updated data can always be read out by reading with a period 192 times the period of the input sampling frequency. The processing load on the micro-controller can be reduced by setting the E/INT pin to interrupt the output and using the update flag interrupt to read out the data. This flag is output when a comparison of the first 48bits of the current data and the data for the previous block indicates that they are the same.
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WM8803
DO7 DO6 DO5 DO4 DO3 DO2 0 DO1
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DO0
0 8 16 24 32 40 48 56 64 72 80
0 Address Track Index Minute Second Frame Zero abs minute abs second abs frame
0 Address Track Index Minute Second Frame Zero abs minute abs second abs frame
0 Address Track Index Minute Second Frame Zero abs minute abs second abs frame
0 Address Track Index Minute Second Frame Zero abs minute abs second abs frame
0 Control Track Index Minute Second Frame Zero abs minute abs second abs frame
CRC Control Track Index Minute Second Frame Zero abs minute abs second abs frame
CRC Control Track Index Minute Second Frame Zero abs minute abs second abs frame
Control Track Index Minute Second Frame Zero abs minute abs second abs frame
Table 24 Output Register: Sub-code Q Data with CRC Flags Output (0xED)
The cyclic redundancy code (CRC) is a set of flags that indicates the correctness of the 80bits of sub-code Q data. Note that the same data is output for both the DO0 and DO1 CRC flags. When sub-code Q data is included in the input data, the result of the CRC calculation can be read out along with the data. To read out the sub-code Q data, the data must be read out with INTQSY set as the E/INT interrupt output function, and the IC must be set up to output the load signal. When sub-code Q data is detected, the E/INT signal will output a high level or a high-level pulse. The sub-code Q data is updated on each rising edge on the E/INT signal. Applications must complete readout of this data within 13.3ms (standard speed) or 6.6ms (2 x speed) of the rising edge of the E/INT signal.
CRC
OUTPUT CONDITIONS
L H
Table 25 CRC Flag Output
Errors were found in the sub-code Q data. The sub-code Q data is correct.
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WM8803
SAMPLE APPLICATION
The power supply pin de-coupling capacitors (0.1F and 10F) should be located as close as possible to the WM8803. Use ceramic and good quality electrolytic capacitors respectively, with good high-frequency characteristics for these components. Use a capacitor with a minimal thermal coefficient for the PLL loop filter capacitor. There are no constraints on the NC pin levels. IC operation will not be affected by leaving them open or by holding them fixed at particular levels.
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WM8803 RECOMMENDED EXTERNAL COMPONENTS
R4 C1
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R3 C1 1 XIN 24
XOUT
2 3 4 5
ERROR PD NC CE CL DI DO E/INT AUDIO
SDIN 23 SDATAO 22 LRCLK 21
Audio Interface
BCLK 20 CLKOUT 19
CPU Interface
6 7 8 9 10
WM8803CDT
DGND 18
AGND 17 NC 16
+
AGND
+
C4 LPF R0 11 12 C0 R1 15
C5
C4
C5
AVDD
UGPI RXIN
AVDD 14 DVDD 13
DVDD C3
R5 C2
AGND
R2
NOTES:
1. AGND and DGND should be connected as close to the WM8803 as possible. 2. C2, C3, C4, and C5 should be positioned as close to the WM8803 as possible. 3. Capacitor types should be carefully chosen. Capacitors with very low ESR are recommended for optimum performance.
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WM8803
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT REFERENCE SUGGESTED VALUE USE NOTES
R0 R1 R2 R3 R4 R5 C0 C1 C2 C3 C4 C5
50 to 1k 75 50k to 100k 1M 150 to 330 * 0.01 to 0.1F 1p to 33pF * * Over 1F 0.1F
-- Coaxial terminator Input amplifier feedback Oscillator amplifier feedback Oscillator amplifier current limited PLL loop filter AC coupling Oscillator element load PLL loop filter PLL loop filter Power supply de-coupling Power supply de-coupling NP0 special ceramic capacitor Film capacitor Ceramic capacitor Electrolytic capacitor Ceramic capacitor Tolerance: 5%
Table 26 Recommended Component Values Note: * Refer Table 4
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WM8803 PACKAGE DIMENSIONS
DT: 24 PIN TSSOP (6.5 x 6.4 x 1.0 mm)
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DM031.B
b
24
e
13
E1
E
GAUGE PLANE 1
D
12
c A A2 A1 -C0.1 C
SEATING PLANE
L
Symbols A A1 A2 b c D e E E1 L MIN ----0.03 0.17 0.10 6.4 6.15 4.30 0.30 o 0
Dimensions (mm) NOM ----0.08 1.00 0.22 0.15 6.50 0.50 BSC 6.4 BSC 4.40 0.50 -----
MAX 1.20 0.18 0.32 0.25 6.95 6.65 4.50 0.70 o 10
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION.
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WM8803
IMPORTANT NOTICE
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QW
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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